BaseDraft
CWE-1303Non-Transparent Sharing of Microarchitectural Resources
Category: logic
Description
Hardware structures shared across execution contexts (e.g., caches and branch predictors) can violate the expected architecture isolation between contexts.
Common consequences· 1
- Confidentiality — Read Application Data, Read MemoryMicroarchitectural side-channels have been used to leak specific information such as cryptographic keys, and Address Space Layout Randomization (ALSR) offsets as well as arbitrary memory.
Potential mitigations· 2
- [Architecture and Design]Microarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.
- [Requirements]Microarchitectural covert channels can be addressed using a mixture of hardware and software mitigation techniques. These include partitioned caches, new barrier and flush instructions, and disabling high resolution performance counters and timers.
Related CAPEC attack patterns· 1
References
Exploits (incoming)1
| Type | Target | Confidence | Tier |
|---|---|---|---|
| AttackPattern | Exploitation of Transient Instruction Executioncapec-663 | 100% | live |
Compliance frameworks addressing this (incoming)1
| Type | Target | Confidence | Tier |
|---|---|---|---|
| ComplianceControl | owasp_llm_top10-llm03 | 100% | live |
Related by meaning· 6
Nearest entities by semantic similarity across the cs-graph corpus.