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CWE-1421Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution

Category: data-exposure

Description

A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.

Common consequences· 1

  • Confidentiality — Read Memory

Potential mitigations· 5

  • [Architecture and Design]
  • [Architecture and Design]
  • [Architecture and Design]
  • [Architecture and Design]
  • [Architecture and Design]

References

  1. https://cwe.mitre.org/data/definitions/1421.html

Related by meaning· 6

Nearest entities by semantic similarity across the cs-graph corpus.

CWE
Exposure of Sensitive Information caused by Incorrect Data Forwarding during Transient Execution
CWE
Exposure of Sensitive Information during Transient Execution
CWE
Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution
CWE
Information Exposure through Microarchitectural State after Transient Execution
CWE
Non-Transparent Sharing of Microarchitectural Resources
CWE
Improper Access Control Applied to Mirrored or Aliased Memory Regions
Sourced from MITRE CWE 4.20. Curated for EU compliance use cases by Adam Lundqvist, Founder at SQUR.