BaseIncomplete

CWE-1281Sequence of Processor Instructions Leads to Unexpected Behavior

Category: other

Description

Specific combinations of processor instructions lead to undesirable behavior such as locking the processor until a hard reset performed.

Common consequences· 1

  • Integrity / Availability — Varies by Context

Potential mitigations· 2

  • [Testing]Implement a rigorous testing strategy that incorporates randomization to explore instruction sequences that are unlikely to appear in normal workloads in order to identify halt and catch fire instruction sequences.
  • [Patching and Maintenance]Patch operating system to avoid running Halt and Catch Fire type sequences or to mitigate the damage caused by unexpected behavior. See [REF-1108].

Related CAPEC attack patterns· 1

CAPEC-212

References

  1. https://cwe.mitre.org/data/definitions/1281.html

Exploits (incoming)1

TypeTargetConfidenceTier
AttackPatternFunctionality Misusecapec-212100%live

Related by meaning· 6

Nearest entities by semantic similarity across the cs-graph corpus.

CWE
Improper Lock Behavior After Power State Transition
CWE
Improper Prevention of Lock Bit Modification
CWE
Insufficient Granularity of Address Regions Protected by Register Locks
CWE
Improper Handling of Faults that Lead to Instruction Skips
CWE
Semiconductor Defects in Hardware Logic with Security-Sensitive Implications
CWE
Uninitialized Value on Reset for Registers Holding Security Settings
Sourced from MITRE CWE 4.20. Curated for EU compliance use cases by Adam Lundqvist, Founder at SQUR.