CVE-2020-24512EPSS p30.3%

CVE-2020-24512CVE-2020-24512

intel / microcode

Description

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

Scoring

CVSS 3.3 ()
VectorCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:L/I:N/A:N
EPSS0.38% probability of exploitation · percentile 30.3% · 2026-10-10T12:00:23Z
Last modified2026-10-08
Sourced from NVD + FIRST.org EPSS. Curated for EU compliance use cases by Adam Lundqvist, Founder at SQUR.